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? semiconductor components industries, llc, 2015 july, 2015 ? rev. 2 1 publication order number: NCP81178/d NCP81178 secondary synchronous rectifier driver for forward converters the NCP81178 is a secondary?side synchronous rectifier driver designed for isolated power converters, especially actively clamped forward and fly?back, and asymmetric half?bridge converters. the NCP81178 drives two n?channel mosfets on the secondary side in a complementary manner. it accepts a pwm input signal derived from the secondary winding or an auxiliary winding on the main power transformer. it can also take a pwm signal from the primary?side controller through a pulse transformer or other isolators. features ? n?channel synchronous rectifier mosfet driver ? pwm input derived from a winding on the main transformer or directly from a pulse transformer ? internally generated pwm threshold voltage that can be programmed externally ? pre?bias startup capability ? primary shutdown detection ? frequency detection window ? wide vin/vcc range: 4.5 v to 14 v ? 6 v/150 ma ldo for vcc supply ? 4.5 a/3.8 a sink and 3 a source drive capability ? 12 ns pwm propagation time ? 12 ns rise time/10 ns fall time at c l = 4700 pf @ v cc = 6 v ? vcc under?voltage lockout ? will support converter output voltages as high as 28 v ? pb?free 10?pin dfn 3 mm x 3 mm package ? this is a pb?free device typical applications ? high?ef ficiency isolated dc/dc power supplies ? server power, 48 v telecom and data?com applications device package shipping ? ordering information NCP81178mntxg dfn10 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. dfn10 mn suffix case 506aa marking diagram 1 81178 alyw a = assembly location l = wafer lot y = year w = work week = pb?free package (note: microdot may be in either location) flag 11 gnd 1 sddet 2 rramp 5 pwm 4 pwmth 3 pbss 6 7 8 9 10 vin gfr dl gfw vcc pin connections (top view) www. onsemi.com
NCP81178 www. onsemi.com 2 sddet rramp pwm pbss pwmth vin vcc gfw dl gfr r ramp q fr q fw vin 5v ? 14v r pbss vout c pbss gnd figure 1. typical application circuit ? secondary synchronous rectifier driver
NCP81178 www. onsemi.com 3 ldo regulator (6 v ) minimum off0 timers, non? overlap and driver logic slow _ ramp generator frequency detection vin vcc gfr gfw pwm pwmth 1.25 v rramp pbss sddet 1 .25 v frequency fault sddet fault sddet fault 10 7 8 6 1 2 3 4 5 9 dl fast _ ramp generator fault pwm_d fault flag 11 gnd 4.3 v hysteresis 400 mv frequency fault vcc uvlo comparator shutdown detection comparator prebias soft?start comparator 1 .25 v pbss onset threshold comparator vcc uvlo sddet control pwm _ d vcc _ uvlo pwm _ d slow ramp slow ramp dl pulldown control pwm_d vcc_uvlo pbss< 3 v slow_ramp 3v pbss < 3 v figure 2. simplified block diagram
NCP81178 www. onsemi.com 4 pin function description pin no. pin name description 1 sddet primary shutdown detection. when the voltage on this pin exceeds the shutdown threshold, the driver shuts down. if valid pwm pulses resume and vcc is above uvlo threshold, the driver will go through a restart process. 2 rramp ramp slope setting for the ramp used in pre?bias start control. this pin also sets the upper and lower boundaries of the frequency detection window. connect a resistor from this pin to gnd (see application information section for selecting resistor values). 3 pbss pre?bias startup ramp voltage setting pin. pulling pbss voltage below the pbss onset threshold voltage disables both gate drives. 4 pwmth pwm threshold voltage. 5 pwm pwm input 6 gfr forward rectifier gate drive 7 dl dummy load function. discharges the output voltage during startup. to use this function, connect a re- sistor from this pin to the output voltage. 8 gfw freewheeling rectifier gate drive 9 vcc ldo output. a ceramic capacitor within the range of 0.1 f and 4.7 f must be placed between this pin and ground. 10 vin ldo input 11 gnd ground. absolute maximum ratings (note 1) rating symbol min max unit ldo voltage range vcc, vin ?0.3 16 v gate drive output voltage range (dc) gfr, gfw ?0.3 16 v gate drive output voltage range (transient, 100 ns) gfr, gfw ?5 v sddet input sddet ?0.3 32 v dl input (dc) dl ?0.3 32 v dl input (transient, 200 ns) dl ?1 v pwm input pwm ?1 30 v pwmth input pwmth ?1 3 v pbss pbss ?0.3 vcc + 0.3 v rramp input rramp ?0.3 3 v maximum junction temperature t j(max) ?55 150 c storage temperature range tstg ?65 150 c esd capability, human body model (note 2) esd hbm 2 kv moisture sensitivity level msl 1 ? lead temperature soldering reflow (smd styles only), pb?free versions (note 3) t sld 260 peak c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. refer to electrical characteristics and application information for safe operating area. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec?q100?002 (eia/jesd22?a114) latchup current maximum rating: 150 ma per jedec standard: jesd78 3. for information, please refer to our soldering and mounting techniques reference manual, solderm/d.
NCP81178 www. onsemi.com 5 thermal characteristics (note 4) rating symbol value unit thermal characteristics, dfn10, 3x3 mm (note 5) thermal resistance, junction?to?air thermal resistance, junction?to?case r ja r jc 55 7.5 c/w 4. refer to electrical characteristics and application information for safe operating area. 5. values based on copper area of 645 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate. operating ranges (note 6) rating symbol min typ max unit switching frequency fsw 100 1200 khz ldo input voltage (note 7) vin 5 14 v external supplied dc source (no dc source on vin) vcc 4.5 14 v external ldo output capacitance c vcc 0.22 1 4.7 uf pwm low pwm_lo ?0.3 1 v pwm high pwm_hi 4 26 v sddet & dl sddet, dl 30 v junction temperature t j ?40 125 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 6. refer to electrical characteristics and application information for safe operating area. 7. ldo input voltage must be greater than or equal to 7 v to ensure performance specified in table 5. electrical characteristics . electrical characteristics v cc = 6 v, f sw = 100 khz to 1.2 mhz, for typical values t a = 25 c, for min/max values t a = ?40 c to 125 c; unless otherwise noted. (notes 8, 9 and 10) parameter test conditions symbol min typ max unit ldo and uvlo vcc voltage regulation vin = 7 v ? 14 v, i vcc = 0?150 ma 5.7 6.0 6.3 v vcc current limit 150 ma vcc uvlo positive?going vcc 4.1 4.3 4.5 v vcc uvlo hysteresis 400 mv shutdown detection (sddet) sddet rising threshold sddet_th 1.22 1.26 1.30 v internal discharge transistor rds(on) 100 pwm threshold (pwmth) pwmth rising hysteresis (note 11) 50 mv pwmth falling hysteresis (note 11) 50 mv pwm threshold (pwmth2) pwmth2 rising 2.4 3.0 3.6 v pwmth2 hysteresis 1.0 v pbss threshold pbss_onset_th when gfr and gfw are enabled 1.22 1.25 1.28 v internal discharge transistor r ds(on) 100 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 8. refer to the application information section. 9. values based on design and/or characterization. 10. 4.7nf driver load capacitance 11. guaranteed by design and/or characterization. not production tested. 12. frequency blanking applied to first valid rising and falling edges of pwm per switching cycle.
NCP81178 www. onsemi.com 6 electrical characteristics v cc = 6 v, f sw = 100 khz to 1.2 mhz, for typical values t a = 25 c, for min/max values t a = ?40 c to 125 c; unless otherwise noted. (notes 8, 9 and 10) parameter unit max typ min symbol test conditions pbss threshold pbss discharge threshold 200 mv slow_ramp thresholds ceiling threshold voltage frmp_h 3.4 3.5 3.6 v bottom threshold voltage (note 11) frmp_l 0.46 0.5 0.54 v frequency detection window lower boundary to upper boundary ratio rramp = 130 k 0.50 0.56 0.62 lower frequency limit 1 rramp = 619 k (100 khz nominal frequency) (note 10) 63 70 77 khz upper frequency limit 1 117 130 143 khz blanking time 1 (note 12) 348 450 552 ns lower frequency limit 2 rramp = 130 k (450 khz nominal frequency) 284 315 347 khz upper frequency limit 2 527 586 645 khz blanking time 2 (note 12) 140 200 260 ns lower frequency limit 3 rramp = 47.5 k (1.2 mhz nominal frequency) (note 11) 756 840 924 khz upper frequency limit 3 1404 1560 1716 khz blanking time 3 (note 12) 77 100 123 ns dummy load internal discharge transistor r ds(on) 10 20 sink current capability dl = 3 v, t a = 25 c 0.3 a dl disabling pbss threshold voltage pbssth2 3.0 v number of ramp cycles to keep dl on for each detected pwm pulse 128 cycles gate driver gfr gfr peak sink current (note 11) gfr = 3 v, v cc = 6 v 3.8 a gfr peak source current (note 11) gfr = 3 v, v cc = 6 v 3 a gfr sink resistance v cc = 6 v, sink current = 200 ma 0.91 gfr source resistance v cc = 6 v, source current = 200 ma 0.91 rise time (note 11) 10% to 90%, cgate = 4.7 nf, v cc = 6 v 12 ns fall time (note 11) 90% to 10%, cgate = 4.7 nf, v cc = 6 v 10 ns minimum off time, within pwm falling edge blanking window fsw = 100 khz (note 11) 300 ns fsw = 450 khz 110 150 195 ns fsw = 1.2 mhz (note 11) 75 ns minimum off time, outside of pwm falling edge blanking window (note 11) 75 ns gate driver gfw gfw peak sink current (note 11) gfw = 3 v, v cc = 6 v 4.5 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 8. refer to the application information section. 9. values based on design and/or characterization. 10. 4.7nf driver load capacitance 11. guaranteed by design and/or characterization. not production tested. 12. frequency blanking applied to first valid rising and falling edges of pwm per switching cycle.
NCP81178 www. onsemi.com 7 electrical characteristics v cc = 6 v, f sw = 100 khz to 1.2 mhz, for typical values t a = 25 c, for min/max values t a = ?40 c to 125 c; unless otherwise noted. (notes 8, 9 and 10) parameter unit max typ min symbol test conditions gate driver gfw gfw peak source current (note 11) gfw = 3 v, v cc = 6 v 3 a gfw sink resistance v cc = 6 v, sink current = 200 ma 0.91 gfw source resistance v cc = 6 v, source current = 200 ma 0.91 rise time (note 11) 10% to 90%, cgate = 4.7 nf, v cc = 6 v 12 ns fall time (note 11) 90% to 10%, cgate = 4.7 nf, v cc = 6 v 8 ns minimum off time, within pwm rising edge blanking window (note 11) fsw = 100 khz (note 11) 300 ns fsw = 450 khz 110 150 195 ns fsw = 1.2 mhz (note 11) 75 ns minimum off time, outside of pwm rising edge blanking window (note 11) 75 ns minimum dead times t dt_gfwl_to_gfrh , delay time from gfw going low to gfr going high (note 11) 90% of gfw to 10% of gfr 0 5 10 ns t dt_gfrl_to_gfwh , delay time from gfr going low to gfw going high (note 11) 90% of gfr to 10% of gfw 0 5 10 ns propagation delay times t pd_pwm_r , propagation delay from pwm going high to gfw going low (note 11) pwm crossing pwmth to gfw falling at 90% 0 12 22 ns t pd_pwm_f , propagation time from pwm go- ing low to gfr going low (note 11) pwm crossing 2 v to gfr falling at 90% 0 21 31 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 8. refer to the application information section. 9. values based on design and/or characterization. 10. 4.7nf driver load capacitance 11. guaranteed by design and/or characterization. not production tested. 12. frequency blanking applied to first valid rising and falling edges of pwm per switching cycle.
NCP81178 www. onsemi.com 8 application information NCP81178 is a secondary?side synchronous rectifier driver designed for isolated power converters, especially actively clamped forward converters. the NCP81178 drives two n?channel mosfets on the transformer secondary side in a complementary manner. it accepts a pwm input signal derived from the secondary winding or an auxiliary winding on the main power transformer. the NCP81178 can also operate with a pwm signal from the primary?side controller through a pulse transformer or other isolator. the pwm threshold voltage on pin pwmth is internally generated from the pwm input voltage and vcc voltage using a signal conditioning circuit. the pwmth voltage is used as the pwm rising and falling thresholds. pwmth is compared with the pwm input voltage to generate an internal pwm signal used to control the gate drive timings. the NCP81178 driver implements a pre?bias startup feature that allows the converter to start into a pre?biased output voltage. the NCP81178 implements a shutdown detection function to detect a primary shutdown. when the voltage on sddet pin exceeds the shutdown threshold, the gate drives are turned off immediately and the NCP81178 will go through a restart process when v cc is above uvlo threshold and valid pwm pulses resume. the NCP81178 also includes a switching period/frequency window detection function. the detection window boundaries are set with a rramp resistor. when the detected switching frequency falls out of this window, the gate drives are turned off immediately and NCP81178 will go through a restart process when vcc is above uvlo threshold and valid pwm pulses resume. the NCP81178 incorporates key protection features such as v cc under voltage lockout. the pbss pin can also be used to rapidly enable or disable the driver outputs from an external signal. pwm input the pwm input to the NCP81178 can be transmitted from a primary pwm controller with a pulse transformer. the pwm signal can also be derived from a winding on the main isolation power transformer. in the latter case, a pulse transformer is not needed and the system cost can be reduced. figure 3 shows a circuit example which uses a voltage shaping circuit to extract the pwm signal from an auxiliary winding on the main transformer. pwm figure 3. pwm signal from an auxiliary winding pwm threshold and gate drive logic the pwm threshold voltage, pwmth, is generated internally from the pwm input signal using a voltage conditioning circuit. figure 4 shows the internal circuitry that generates the pwmth threshold voltage from the pwm input. there is a resistor divider network that scales down the pwm signal by a 5:1 ratio. this circuit creates a pwm rising threshold at around 0.2 v (equivalent to 1 v without the 5:1 scale factor), while the pwm falling threshold is set to the pwmth2 falling threshold of 2 v, typical. this approach enables the driver pwm circuit to detect the primary switching actions as early as possible, which is very important for achieving efficient and reliable synchronous rectification on the secondary. secondly, the pwmth waveform is kept away from the voltage ringing of the pwm input voltage. thirdly, the bottom part (i.e. the pwm rising threshold) and the top part (i.e. the pwm falling threshold) of the pwmth voltage closely follow the pwm input voltage even during extremely fast and lar ge transients which may cause very large swings on pwm input voltage. this ensures the pwm detection logic is always valid for any operating conditions. this internal pwmth circuit is optimized to work up to 1.2 mhz switching frequency for a majority of the applications.
NCP81178 www. onsemi.com 9 50k 12.5k 150k 12.5k pwmth 1.25v pwm_in pwm 13p 100k figure 4. pwm and pwmth internal circuitry pwm_in pwmth pwmth2 pbss_pwm gfr gfw figure 5. simplified driver logic block diagram as shown in figure 5, by comparing the pwm input voltage with pwmth, an internal pwm signal, pwm_d, is obtained to generate the gate drives. the forward rectifier gate drive (gfr) is directly in phase with pwm_d, while the freewheeling rectifier gate drive (gfw) is 180 out of phase with pwm_d and gfr. refer to figure 6 for circuit waveforms, pwm logic and gate drive timing diagrams. to reduce the chance of the gate outputs falsely triggering a frequency fault due to ringing on the pwm signal, the NCP81178 uses blanking windows after there is a change in state of gfr and gfw. after a pwm_d rising edge, a blanking timer is initiated that prevents a frequency detection fault from being declared until the blanking timer expires. the duration of this blanking timer changes with the pwm switching frequency. a similar blanking timer is initiated during the pwm_d falling edge, whose duration timer is also dependent on the pwm switching frequency. the NCP81178 uses minimum off timers on gfr and gfw, which restrict the shortest time gfr and gfw can be in the low state before changing to a high state. a short off pulse can result in a voltage spike at the pins of gfr and gfw, the magnitude of which depends on the trace inductance between the driver outputs and the gate of the mosfets. the minimum off timers help to prevent a voltage spike that can be large enough to damage the output devices on gfr and gfw. the duration of the minimum off timers depends on whether the NCP81178 is in one of the aforementioned b lanking timers. when within the blanking timer, the duration of the minimum off timer changes with the pwm switching frequency. at a switching frequency of 100 khz the typical minimum off timer is 300 ns, while at 1.2 mhz the typical minimum off timer is 75 ns. when outside of the blanking timers, the duration of the minimum off timer is fixed at a typical 75 ns, and does not change with the pwm switching frequency.
NCP81178 www. onsemi.com 10 figure 6. gate drive timing diagram t pd _pwm_r t pd _pwm_f pwmth pwmth2 pwm gfr gfw vds (q_main) gate (q_ac) gate (q_main) t dt _gfwl_to_gfrh pwmth2 ? 1 v hysteresis
NCP81178 www. onsemi.com 11 shutdown detection (sddet) the shutdown detection function allows the primary?side controller to send a shutdown signal to the secondary?side driver. as shown in the t ypical application circuit in figure 1, the sddet pin is used to detect an increase in volt?seconds in the main transformer. an rc ramp circuit is connected from sddet to the freewheeling rectifier drain, dfw, or to an auxiliary winding on the main transformer. when the voltage on sddet exceeds the shutdown detection threshold voltage, gfr and gfw are immediately pulled low and pbss is discharged. when valid pwm pulses resume and v cc is above uvlo, the NCP81178 will go through a restart process. this is a non?latching shutdown. using the shutdown detection function ensures both gate drives to turn off when there is positive current through the output inductor. turning off both gate drives when there is negative current through the freewheeling fet could result in excessive voltage transients across the freewheeling fet. pre?bias startup the ncp81 178 implements a pre?bias startup function. a rc circuit (r pbss and c pbss ) connected to the pbss pin sets the pre?bias startup ramp voltage to define the transition process from diode rectification mode to synchronous rectification mode. during pre?bias startup, c pbss is charged by resistor r pbss , connected from v cc to pbss. initially, when v cc reaches uvlo and the NCP81178 is activated, the pbss voltage is first discharged and then starts to charge up. when the pbss voltage is lower than the pbss onset threshold voltage (pbss_onset_th), both gate drives are pulled low. once the pbss voltage rises above pbss_onset_th, the gfr output follows the pwm input while at the same time the pre?bias process is initiated and the gate drive pulse width of the freewheeling gate drive gradually increases from 0 to its final steady state value until the secondary rectifier fully enters synchronous rectification mode. a resistor connected from rramp to ground sets the discharge ramp slope for a ramp voltage within the NCP81178. this discharge ramp (slow_ramp) together with the pbss ramp sets the gfw pulse width in the pre?bias startup transition process. in the pre?bias startup process the rising edge of the gfw pulse gradually expands backward until it meets the falling edge of the gfr pulse. pulling the pbss voltage below the pbss_onset_th voltage disables both gate drives. refer to figure 7 for the key timing waveforms for pre?bias start. vcc uvlo vcc pwm pbss_onset_th pbss_pwm gfr gfw pbss slow_ramp figure 7. key waveforms and timings for pre?bias start
NCP81178 www. onsemi.com 12 switching period/frequency detection the NCP81178 uses internally?generated ramps to determine if the detected switching frequency differs from the expected switching frequency. the expected switching frequency is programmed by the value of the rramp resistor. the rramp value set the slopes of both slow_ramp and fast_ramp. slow_ramp, see figure 9, is used to determine if the switching period is longer than 1.3 times the nominal period, while fast_ramp, see figure 10, is used to determine if the switching period is less than 0.7 times the nominal period. if the period is determined to be either greater than 1.3 times or less than 0.7 times the nominal period, a frequency fault will be declared, disabling both gate drives and discharging pbss. the driver will go through a restart when valid pwm pulses are received and vcc is above uvlo. figure 8 shows the regions where a frequency fault will occur. to prevent ringing on pwm from triggering a false frequency fault, the NCP81178 uses blanking windows at the rising and falling edges of pwm. the blanking windows start at the rising and falling edge of the internally?derived pwm signal (pwm_d), and its duration is dependent on the switching frequency set by rramp. at a switching frequency of 100 khz the blanking timer is 450 ns, while at 1.2 mhz the blanking timer is 100 ns. when within a blanking window, gfr and gfw respond normally to pwm_d, but a frequency fault will not be declared regardless of how close together two pwm_d rising edges are. 0.7*ts 1.3*ts rising edge blanking timer : fault detection region time pwm_d falling edge blanking timer ts figure 8. switching period/frequency detection region the rramp resistor sets the nominal switching frequency. the value of the rramp resistor is determined by the following equation: for frequencies 300 khz: for frequencies 300 khz: in the above equation, f is the target switching frequency, in khz. figure 9 shows how the switching period/frequency detection function detects a switching period longer than 1.3 times a nominal switching period. if slow_ramp is allowed to reach slow_freq_threshold, it indicates that either a missing pulse or a primary shutdown condition is detected and a frequency fault is declared. gfr and gfw are immediately pulled low and the pbss voltage is discharged. the driver will go through a restart process when valid pwm pulses resume and vcc is above uvlo. the value of the rramp resistor sets the slope of slow_ramp. the rramp value is chosen such that when slow_ramp is reset to the ceiling voltage at the start of each switching cycle, slow_ramp is not allowed to reach slow_freq_threshold during the valid frequency range. the missing pulse detection feature is very important to make the pre?bias startup function adaptive. when the isolated dc converter output is pre?biased during startup, before the secondary feedback loop reference voltage rises above the sensed voltage, the primary side pwm controller puts out very narrow pwm pulses, and there are multiple time intervals where the pwm pulses are missing while waiting for the secondary side circuit, including the bias voltage and feedback loop, to come up. during these multiple intervals where the pwm pulses are missing, the pbss voltage is discharged. this ensures the pbss voltage starts to charge up until the secondary side circuit has overcome the pre?bias voltage and is ready for a normal startup process without further missing pwm pulses. this ensures the pre?bias function works consistently for wide line and load conditions and pre?bias voltage variation. figure 10 shows how a switching period shorter than 0.7 times the nominal switching period is detected. fast_freq_threshold represents the voltage on fast_ramp that is equivalent to 0.7 times the nominal switching period. the value of the rramp resistor sets the slope of fast_ramp. if a pwm rising edge is detected before fast_ramp has reached fast_freq_threshold, a frequency detection fault is triggered. the pbss voltage is discharged, the gate drives are disabled, and the driver will go through a restart process when valid pwm pulses resume and v cc is above uvlo.
NCP81178 www. onsemi.com 13 pwm gfr gfw slow_ramp pbss slow_freq_threshold rising edge blanking timer time falling edge blanking timer figure 9. slow frequency detection leading to a shutdown pwm gfr gfw fast_ramp pbss fast_freq_threshold rising edge blanking timer time falling edge blanking timer figure 10. fast frequency detection leading to a shutdown
NCP81178 www. onsemi.com 14 ldo regulator the NCP81178 integrates a ldo regulator to generate a regulated v cc voltage from an unregulated or loosely regulated dc voltage on the vin pin. the regulated voltage on the ldo output vcc pin is nominally 6 v. the ldo regulator supplies the gate drive energy and the ic bias power in the NCP81178. it is capable of delivering at least 150 ma current. to stabilize the feedback loop of the ldo regulator, a ceramic capacitor with a value between 0.22 uf and 4.7 uf is required to be placed between vcc and pgnd. when vcc pin is connected to a dc source with a voltage higher than the ldo regulated output voltage, the ldo regulator is disabled and the NCP81178 is powered from the external dc source. uvlo the NCP81178 has an under?voltage lock?out feature on the v cc supply voltage. the driver outputs will be disabled until vcc exceeds the uvlo threshold. there is a hysteresis, typically 400 mv, on this threshold. dummy load function during st artup, the dl pin wi ll dischar ge the voltage at the output of the power supply, if dl is connected to the output voltage with a resistor. once vcc is above the uvlo threshold voltage, the dl pin will start sinking current once: 1. the voltage on pbss is below 3 v. 2. a valid pulse is detected on pwm. dl will continue to pull low for 128 slow_ramp cycles after the last valid pwm pulse after pbss rises above 3 v. exposed pad the exposed metal pad at the bottom of the package is connected to gnd and aids in enhancing the thermal performance of the package.
NCP81178 www. onsemi.com 15 figure 11. v cc regulation vs. v in (t j = 25 c) figure 12. v cc regulation vs. temperature (v in = 10 v) figure 13. switching supply current vs. temperature (v cc = 6 v, 4.7 nf loads, 450 khz) figure 14. v cc uvlo vs. temperature figure 15. upper frequency detect vs. temperature (rramp = 130 k ) figure 16. lower frequency detect vs. temperature (rramp = 130 k )
NCP81178 www. onsemi.com 16 figure 17. upper frequency detect vs. v cc (t j = 25 c) figure 18. lower frequency detect vs. v cc (t j = 25 c)
NCP81178 www. onsemi.com 17 package dimensions ??? ??? ??? case 506cl issue o 10x seating plane l d e 0.10 c a a1 e d2 e2 b 1 5 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. for device opn containing w option, detail b alternate construction is not applicable. b a 0.10 c top view side view bottom view pin one reference 0.05 c 0.05 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 3.00 bsc d2 2.40 2.60 e 3.00 bsc e2 1.40 1.60 e 0.50 bsc l 0.25 0.45 l1 0.00 0.03 detail a 2x 2x detail b l1 detail a l alternate terminal constructions l ?? ?? *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 3.30 0.50 0.57 10x dimensions: millimeters 0.32 2.70 pitch 1.70 10x 1 package outline recommended note 4 k 0.25 ??? on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81178/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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